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LD7271 09/ 13/ 201 1 1 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 smart photoflash capacitor charger with integrated mos rev 02 general description t he LD7271 is an ide a l char ge contro l ic for flash un it s, featurin g i n ter nal s o f t st art, adj ust abl e ch a r gin g curre nt and o u tput vol t age. it provid es a charg i n g algor ithm to spee d up th e c harg i ng w i th h i gher ef fic i e n c y . t he ld7 2 7 1 can o per ate i n des ired c o n st ant peak c u rrent of ei ght dif f ere n t levels bet w e e n 0.6a and 1.3a, b y clocking th e charge pi n. t he LD7271 i s availa ble in a space-savi ng w d f n -8l 2mm x 2mm p a ckag e an d is i dea l for dsc flash un it. g patented features ? 1.8v~ 6 v battery volt age r a n ge ? adjusta b le out put voltag e ? adjusta b le in p u t current ? integrated 47v po w e r mos ? f a lse t r iggerin g preventi on ? soft start ? output voltag e overcharge pr otection ? high effici enc y applications ? dsc flash u n i t ? camera p hone typical application r1 1 30k r2 1 30k r3 1k r p 1 f c1 10 f~ 22 f c s 1n f* c2 72 f d 1/ft 01p80 * if lx pin spi k e is over 4 7 v, p l ease a dd c s to red u ce spike . c s 1nf is reco mm ende d. r n fig.1 http://
LD7271 2 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 pin configuration do n e # ou t n ou t p vc c lx charge fb 8 7 6 5 1 2 3 4 w d f n - 8 ( 2 mm x 2 m m) a: l d 72 71 : b l a n k s p ac e p: p r o duc ti o n c o de y : y ear c o de w : w eek c o d e t: t h i c k n e s s w : 0. 7 5 m m ( t y p i c al ) trigger a p yw t ordering information pa rt numbe r pa c k a g e top ma rk shipp i ng LD7271gddw wdfn-8l 2x2 green package a ? p 2500 /tape & reel t he ld727 1 is gree n pack age d. pin descriptions pin n a m e function 1 done# charge done indicator. done# is a pus h-pull drain output that pulls low when charge is high and the circuit has finished charging the output capacitor. 2 outn igbt driver sink output pin. 3 outp igbt driver source output pin. 4 vcc input power of ic. bypass with a 1 f ceramic capacitor close to ic gnd. 5 fb output voltage feedback 6 charge charging on/off control. 7 trigger trigger on/off control. 8 lx nmos drain pin. connect to transformer primary as shown in fig.1. ex posed metal pad gnd ic gnd. exposed pad should be solder ed to pcb board with a larger area
LD7271 3 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 block dia g ram absolute maximum ratings vcc, charg e, t r ig ge t r , done#, ou tp, ou t n , pin -0.3v~ 6.5v fb pin -0.45v~ 6 .5v lx pin<200ns -0.3v~ 47v dc -0.3v~ 42v lx c u rre nt 3.3a power dissipation, p d @t a =25 c (wdfn-8l 2 x 2) 606mw package thermal resistance (wdfn-8l 2 x 2), ja 165 c/w operating ambient temperature range -30 c to 85 c operating junction temperature range -30 c to 125 c maximum junction temperature 150 c storage temperature range -50 c to 150 c lea d t e mperature (sol deri ng, 10sec) 260 c esd l e v el (h uma n bo dy mode l ) 2kv esd leve l (ma chin e mode l) 200v cauti on: stresses beyond the ratings specified in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above t hose indicated in the operational sections of this s pecification is not implied.
LD7271 4 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 electrical characteristics (t a = + 2 5 c unless other w i se stated, v cc =3 .3 v) p a r a m e ter conditions min typ m a x units inpu t po w e r operatin g volt age v cc 2.8 5.5 v und e r volta ge lock out (on) 2.65 v und e r volta ge lock out (of f ) 2.55 v shutdo w n c u rrent i cc charge=off, tr igger=off 1.5 3 a nomin a l su ppl y curr ent v cc = 3 .3v, d= 50% 1 ma fb refere nce volt age 1.15 v refere nce volt age t o lera nce -1.5 + 1 .5 % sampl e time of f b detection 225 250 275 ns lx pin on resistance i lx = 1 .3a 250 330 m lx l eak ag e cur r ent vl x= 42v 5 a current setting i ilm1 0.555 0.6 0.645 a i ilm2 * 0.647 0.7 0.753 a i ilm3 * 0.74 0.8 0.86 a i ilm4 * 0.832 0.9 0.968 a i ilm5 * 0.925 1.0 1.075 a i ilm6 * 1.017 1.1 1.183 a i ilm7 * 1.11 1.2 1.29 a i ilm8 * 1.202 1.3 1.398 a igbt dri v er out p on resistance v cc = 3 .1v 2 3 out n of f resistance v cc = 3 .1v 40 50 on/off enab led 1.4 v t r igger on/off disab le d 0.6 v enab led 1.4 v charge on/off disab le d 0.6 v
LD7271 5 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 p a r a m e ter conditions min typ m a x units done# done# output lo w volta ge i done # = 1 ma 0.1 v done# output high vo ltag e i done # =-1 m a, v cc -v done # 0.1 v impedance to gnd char ge pin to gnd 100k t r igger pin to gnd 100k out p pin to g nd 20k out n pin to g nd 20k i pea k clock hi gh a nd l o w t i me of char ge pin subse q u ent pulses 2 s t o tal clock pulse setting time of char ge pin 200 s others t hermal shutd o w n 150 c max on t i me 30 s propa gati on d e la y (t rigger= high) del a y to out p and out n 60 ns * i lm2-8 are guaranteed by design.
LD7271 6 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 typical performan ce characteristics f i g. 2 s of t s t a r t f unc t i on ch1 = v ou t c h3 = do ne # ch4 = i in ch 2 = c h a r g e fi g . 3 t y p i ca l s w i t ch i n g w a ve f o r m ch1 = v ou t ch 2 = v lx ch 4=i lx f i g. 4 t w o le v e l c h a r g i ng c u r r e n t w a v e f o r m ch 4 = i lx ch 2 = ch a rg e f ig. 5 fal s e t r i g ge r i n g p r ev en t i o n ch 1 = cha r g e c h 2 = t r igge r ch 3 = o u t p ch 4 = d o n e # vc c i s r e s e t
LD7271 7 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 f i g. 6 c h a r g i n g w a v e f o r m v b a t = 3 v ch 1 = v ou t ch 2 = v ba t c h 3= d o n e # ch 4 = i in fig. 7 c h ar gi n g w av ef o r m v b a t = 4 . 2 v ch 1 = v ou t ch 3 = d o ne # ch 2 = v ba t ch 4 = i in f i g. 8 s e c o nd ar y d i o de o pe n c i r c u i t v ba t =v cc =4 .2 v ch 1 = v ou t ch 2 = v lx ch3 = d o ne # ch 4 = i lx fig. 9 t1 s e c o nd ar y s i d e s h or t c i r c u i t v ba t =v cc =4 .2 v ch 1=v out ch2=v lx ch 4= i l x fig. 1 0 f b p a t h o p en c i r c ui t ( r 1 or r 2) ch1=v ou t ch 2=v lx ch 3 = do n e # ch4 = i l x f i g . 10 fb path s h o r t c i r c u i t ( r 3 = 0 ) v ba t =v cc =4 . 2 v ch 1 = v ou t ch2 = v lx ch 4 = i lx ch3= d o n e #
LD7271 8 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 f i g . 1 1 p r i m a r y s i d e i n d u c to r s h o r t c i r c u i t v ba t =v cc =4 . 2 v ch 1 = v ou t ch 2 = v lx ch4=i l x
LD7271 9 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 function description adjustable charging current t he primar y side p eak cur r ent is adj ust abl e to eight dif f ere n t levels bet w e e n 0.6a and 1.3a, b y clocking th e charge pi n, w h ich is s h o w n as f i g. 12. t he tot a l chargin g curre nt setting time of charg e clock must be set w i thin 200 s from the first edg e to the last lo w - to-h ig h ed ge. t he minimum puls e w i d t h from lo w - to- h ig h to high-to- l o w must be larg er than 2 s at le a st during curr e n t setting time interval. f i g. 12 i iil m c l ock t i ming d e finitio n transforme r turn rati o a carefull y c hose n transfo rmer can re sult in b e st performa nce o f the ld727 1. also, the turn ratio of the transformer s hou ld b e t a ken into c onsi derati on. t he maximum volt a ge ratin g of the internal nmo s for ld727 1 is 47v . t hus, the turn ratio is obt ai ned b y : spike batmax d1 out v - v - 47 v v n + n: turn ratio of transformer v out : target output voltag e v d1 : the for w a r d voltag e of d1. if v out = 320v , v ba t m ax = 6 v an d v spike =0v , the turn ratio n shou ld b e mo re than 8. in gen eral l y ap pl i cations, the recomme nde d turn ratio is 10 ~ 20. minimum primary indu ct ance t o ensure ac curate o per ati on for th e l d 72 71, the accept a b le pri m ar y in duct a n c e, lp (h), sh oul d meet the follo w i ng formula: pri - pk out -9 p i n v 10 75 2 l i pk-pri : the selecte d min primar y current limit valu e duri ng char gi n g peri od n: turn ratio of transformer v out : target output voltag e
LD7271 10 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 ex 1: n=14, v out = 300v , set primar y si de peak curre nt limit valu e dur i ng op erati on, i ipk- pr i = 0. 6a ? lp 10 h. in most appli cations, it? s recomme nde d to choose a transformer of l p =6 h~15 h for v ba t in the volt ag e rang e of 1.8v~ 6 v . soft start t he sof t st art w i ll el imin ate the inrush c u rrent at the beg inn i n g of charg i ng pr oces s. w hen the output volt a g e is less than 2 0 v , the ld7 2 7 1 w i ll set the lo w e st p eak current limit (0.6a) to charge the cap a cit o r . as output volt ag e rises u p abov e 20 v , the curre nt limit w i ll the n rise up to the set current lev e l. t he adv ant ag e of this control scheme is to l i m it the initia l in rush curre nt an d all o w usi n g a smaller input cap a cit o r . minimum off time of v lx t he accept ab l e min i mum p u l se of vl x sho u ld be larg er than 40 0ns d u r ing the w h ol e chargi ng c y cl e. other w i s e , the f b signal detectio n sche m e of ld72 71 can?t op erate prop erl y and w i ll af fect the accurac y of output volt age detectio n . ti m e t> 4 0 0 n s v lx fig. 1 3 transforme r primary l eakage inductance t he leakage ind u ct ance at the primar y side of the transformer w i l l result in the turn-of f sp ike at l x pi n. t he spike sho u l d not exce ed the d y nam ic rating of the lx pi n. t o restrict it, it? s necessar y to choose a transformer w i t h lo w e r l eak ag e i nduct a nce. transforme r secondary capacita nce an y cap a cit anc e on the secon dar y w i ll sever e l y af fect the ef ficie n c y . t he secon dar y cap a cit anc e is mul t iplie d b y n 2 w h e n reflecte d to the primar y sid e an d ca use it larg er . t h is cap a cit a n ce forms a res ona nt circuit w i th the primar y leak age i n d u ct ance of the tra n sf ormer . t herefore, both th e primar y leak ag e induct a nce and seco nd ar y cap a cit anc e shou ld b e mini mized. as w e l l , the ld7 271 als o buil d s in w i t h over current protectio n of lx pi n to av oid tra n sform e r saturati on cond ition. if the primar y curre n t is over 3a, th en the ic w i l l latch of f and st op s w itching. false triggering preve ntion t he ld727 1 a l so cons ist of false trig geri n g preve n tio n function, w h ich can preve n t igbt from false trigger ing i n case the trigg e r pi n rec e ive s false trig ger i ng p u ls e from dsp duri ng vc c po w e r-on i n terval. see it as f i g. 14.
LD7271 11 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 fig. 1 4 t he signal of igbt gate w i ll b e hig h accor d in g to follo w i n g sequ enc e. 1. vcc>uvlo (on) (t y p ic al 2.6 5 v) 2. char ge pin tur ned to lo w onc e and done# pin turne d to lo w onc e. 3. t r igger pin is h i gh a nd ch arge pin is lo w . maximum on time t o protect agai nst insuf f icie nt current from a poor po w e r source (i e., an almost disch a r ged b a tter y ) a nd un ab le to reach c u rrent l i m it valu e in ti me, the ld 72 7 1 w i l l em plo y maximum on- time function for it. once on-time of ch a r gi n g pe riod ex ce ed s 3 0 s, the ld72 71 w i ll b e latch ed of f in regar dles s of current limi t detection. adjust output voltage a resistor divi d e r can b e con nected to th e center of the dua l dio de to elimin ate the leakag e curr ent af ter the charg i ng c o mpl e tes. f i g.15 s h o w s the ap pli cation circ uit of resistor divider . r1 130k /1% c2 90 f d 1 /chbd 4004 r2 130k /1% r3 1k /1% fig. 1 5 ? ? ? ? ? ? + + = r3 r2 r1 1 1.15 v out it? s not recom m end ed to ch oose a resisto r larger th a n 1k to con n e ct w i th f b to gnd (r3 in f i g. 15), since a larg er resistor w o ul d carr y p a rasitic cap a cit a n ce and af fect the accurac y of v out detection. as w e ll, the s w itching nod es such as lx pin or sec ond ar y sid e of xfmr sh oul d be route d a w a y from f b pin in such ap plic ation as f i g. 2 0 to obt ain acc u r a te v out detection.
LD7271 12 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 output voltage overch arge protec tion as sho w n i n f i g. 1, the f b pin ma y fai l to reach 1.15v during th e char gin g c y cle, n e it her w h en t he r3 is s hort to gnd or r1 (or r2) open. it w i ll cause v out increase contin uo usl y til l over the t a rg et value of ou tput volt age. ld7 271 feat u r es propri e t a r y detecti ng scheme to ef fectivel y av oi d this phe nom eno n. igbt driver ld7 271 emp l o y s s epar ate s ource an d sin k pin of igbt driver, w h ich ena bles th e users to e a sil y me et the requ ireme n t of an y d i fferent igbt applicatio ns. in addition, if vcc is bel o w 2.5 5 v (t yp), out p and out n pin w i l l be 0v even w h e n t r igger pin is toggle d . rectify i ng diode selection it? s preferab le to choose a rectif y i n g di o de w i th l e ss reverse rec o ver y time to mi ni mize the s w itc h in g loss an d incre a se the c harg i ng ef fici en c y . and more, i t w o ul d al lo w suf f icie nt peak reverse volt ag e and peak for w a r d current rating. t he peak rever se volt ag e is w r itten as bel o w . v pk-r = v out +nv ba t +vs pike t he peak for w ard curre nt is as belo w . i pk-sec = ip / n, i p : peak primar y curre nt (a), n: turn ratio interface charge, done# and t r igger ca n be easil y interface d to a microproc essor . t he charge pin is the o n/of f control of charg i n g circuit. h i g h = en ab le , l o w =di sab l e t he done# pin is an i ndic a tor of chargin g and outp u t volt ag e st ate. high= other w i se lo w = the ch argi ng is compl e ted an d cha rge pi n is hig h t he t r igger pin is the on/ o f f control of the strobe to gen erate a l i gh t pulse. h i g h = en ab le , l o w =di sab l e abnormal operation protection ld7 271 featur es man y pr ot ections a gai n st abnormal oper ation, l i ke s second ar y d i od e op en circ uit, feedb ack resistor ope n circuit and prima r y side in ductor short circuit etc. refer it to the figures fr o m f i g. 8~ 1 1 for the actual l y test w a veforms. la y out con s ideration 1. pleas e follo w t he la yo ut gu id e bel o w for hig h volt ag e isolati on to av o i d an y br eak do w n f a il ure. 2. place the c vcc by p a ss cap a citor of 1 f very close to ic gnd. (<5m m) 3. refer to f i g.16 ; please ro ute gnd pla ne or gnd p a th a w ay from nodes of r1, r2 and r3. 4. keep outp u t volt ag e feed bac k net w o rk cl os e to ic and far a w a y fr om an y interfer ence n o d e s or p a ths. 5. place l x pin and gnd pi n w i th l a rg e met a l trace area. 6. t he s w itchin g nodes, such as lx pi n or ano de of rectif y i ng d i od e shoul d be ke pt a w a y from f b pin. 7. pleas e refer t o f i g.16 and t he ev kit for the pcb la yo ut exampl e .
LD7271 13 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 fig. 1 6 re c o mme nde d pcb lay out
LD7271 14 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 pack age information wdfn-8l det a i l x the co n f ig ur a t i o n o f th e p i n 1 i d en t i f i er i s o p t i o nal as ab o v e . dimensions in millimeters dimensions in inch symbols min max min max a 1.900 2.100 0.075 0.083 b 1.900 2.100 0.075 0.083 c 0.650 0.850 0.026 0.033 d 0.150 0.300 0.006 0.012 e 0.550 0.950 0.022 0.037 f 0.5 t yp. 0.02 typ. g 0.190 0.250 0.007 0.01 h 1.150 1.650 0.045 0.065 i 0.000 0.050 0.000 0.002 m 0.300 0.400 0.012 0.016 im portan t n o tice lea dtren d t e chno log y cor p . reserves the right to make ch ang es or corrections to its products at an y time w i th out noti c e. customers sh o u ld ver i f y the d a tashe e ts are current an d co mplete b e fore placi ng or der.
LD7271 15 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 ir profile for smd devices 0 50 100 150 20 0 250 300 te m p . (o c) time ( s ec.) ra mp u p 3oc/ second max. 217 oc 60 ~ 150 seconds peak temp. 260 - 5 / + 0oc , 30 seconds (m ax .) pre hea t 60 ~ 120 seconds 260 217 ra mp do wn 6oc/ second max. item a vera ge ramp-up rate pre-he at (150 ~ 200 c) t i me maint a ined above 2 17 c peak t e mp. ramp-do w n rate req u ire d 3c(max ) /sec 60~ 12 0 sec 60~ 15 0 seco n d s 260 + 0 /-5c 30 seco nds 6c (max) /sec
LD7271 16 le a d trend t e c hnol ogy corpora t ion www . l e a d tren d.co m.t w LD7271- ds-02, sep . 201 1 revision history rev . date cha nge n o tice 00 2/22/20 1 1 original s pec ifi c ation 01 8/10/20 1 1 revision: lx le akag e curre nt cond ition i n ele c trical ch aract e ristics from 47 v to 42v . 02 9/13/20 1 1 revision: t o t a l clock puls e setting time o f charge pi n: 2 0 0 s. ( w as 80 s) shunt do w n cu rrent: 1.5 a ( t y p .) 3.0 a (max . ) ( w as 1.5 a, max )

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